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? 2002 quicklogic corporation www.quicklogic.com 1 ? ? device highlights high performance & high density 36,000 usable pld gates with 204 i/os 300 mhz 16-bit counters, 400 mhz datapaths, 160+ mhz fifos 0.35 m four-layer metal non-volatile cmos process for smallest die sizes high speed embedded sram 14 dual-port ram modules, organized in user-configurable 1,152 bit blocks 5 ns access times, each port independently accessible fast and efficient for fifo, ram, and rom functions easy to use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities interfaces with both 3.3 v and 5.0 v devices pci compliant with 3.3 v and 5.0 v busses for -1/-2/-3/-4 speed grades full jtag boundary scan i/o cells with individually controlled registered input path and output enables figure 1: quickram block diagram 14 ra m blocks 672 hi gh s pee d logic cells interface ql4036 quickram data sheet 36,000 usable pld gate quickram esp combining performance, density and em bedded ram
2 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g architecture overview the quickram family of esps (embedded standard products) offers fpga logic in combination with dual-por t sram modules. the ql4036 is a 36,000 usable pld gate member of the quickram family of esps. quickram esps are fabricated on a 0.35 m four-layer metal process using quicklogic's patented vialink ? tm technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. the ql4036 contains 672 logic cells an d 14 dual port ram modules (see figure 1 ). each ram module has 1,152 ram bits, for a total of 16,128 bits. ram modules are dual port (one read port, one write port) and can be configured into one of four modes: 64 (deep) 18 (wide), 128 9, 256 4, or 512 2 (see figure 4 ). with a maximum of 82 i/os, the ql4036 is available in 144-pin tqfp, 208-pin pqfp, 208-pin cqfp, and 256- pin pbga packages. designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see figure 2 ). this approach allows up to 512-deep configurations as large as 16 bits wide in the smallest quickram device and 44 bits wide in the largest device. software support for the complete quickram family, including the ql4036, is available through two basic packages. the turnkey quickworks ? tm package provides the most complete esp software solution from design entry to logic synthesis, to place and route, to simulation. the quicktools packages provides a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, viewlogic, aldec, or other third-party tools for design entry, synthesis, or simulation. the quicklogic ? tm variable grain logic cell features up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. each cell has a fan- in of 29 including register and control lines (see figure 3 ). figure 2: quickram module bits rdata wdata raddr rdata waddr wdata ram module (1,152 bits) ram module (1,152 bits)
? 2002 quicklogic corporation www.quicklogic.com 3 ql4036 quickram data sheet rev g product summary total of 204 i/o pins 196 bi-directional input/output pins, pci- compliant for 5.0 v and 3.3 v buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins eight low-skew distributed networks two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs?each driven by an input-only pin six global clock/control networks available to the logic cell f1, clock, set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the output enable control?each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance silicon input + logic cell + output total delays = under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz fifo speeds over 160+ mhz
4 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g electrical specifications ac characteristics at v cc = 3.3 v, ta = 25 c (k = 1.00) to calculate delays, multiply the appropriate k factor from table 10: operating range by the following numbers in the tables provided. figure 3: quickram logic cell table 1: logic cell symbol parameter propagation delays (ns) fanout (5) 1 2 3 4 5 t pd combinatorial delay a a. these limits are derived from a representative selection of the slowest paths through the quick- ram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. 1.4 1.7 1.9 2.2 3.2 t su setup time a 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t set set delay 1.0 1.3 1.5 1.8 2.8 t reset reset delay 0.8 1.1 1.3 1.6 2.6 t sw set width 1.9 1.9 1.9 1.9 1.9 t rw reset width 1.8 1.8 1.8 1.8 1.8 qs a1 a2 a3 a4 a5 a6 f1 f2 f3 f4 f5 f6 qs op b1 b2 c1 c2 mp ms d1 d2 e1 e2 np ns qc qr oz az qz nz fz
? 2002 quicklogic corporation www.quicklogic.com 5 ql4036 quickram data sheet rev g figure 4: quickram module table 2: ram cell synchronous write timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 t swa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 t swd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 t swe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 t wcrd wclk to rd (wa=ra) a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 5.0 5.3 5.6 5.9 7.1 table 3: ram cell synchronous read timing symbol parameter propagation delays (ns) fanout logic cells 1 2 3 4 5 t sra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 t hra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 t sre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 t hre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 t rcrd rclk to rd a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 4.0 4.3 4.6 4.9 6.1 wa wd we wclk re rclk ra rd [8:0] [17:0] [8:0] [17:0] mode asyncrd [1:0]
6 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g table 4: ram cell asynchronous read timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 rpdrd ra to rd a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 3.0 3.3 3.6 3.9 5.1 table 5: input-only / clock cells symbol parameter propagation delays (ns) fanout 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 .19 2.0 2.5 3.0 4.5 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t iclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t irst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t iesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 table 6: clock cells symbol parameter propagation delays (ns) fanout a a. the array distributed networks consist of 40 half columns and the global distributed networks con- sist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to eight loads per half column. the global clock has up to 11 loads per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
? 2002 quicklogic corporation www.quicklogic.com 7 ql4036 quickram data sheet rev g figure 5: loads used for t pxz table 7: i/o cell input delays symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 t ioclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t iorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 t iesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 table 8: i/o cell output delays symbol parameter propagation delays (ns) output load capacitance (pf) 3 50 75 100 150 t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a a. these loads are used for t pxz (see figure 5 ) 2.0 - - - - t plz output delay high to tri-state a 1.2 - - - - 1? 1? tphz tplz 5 pf 5 pf
8 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g dc characteristics the dc specifications are provided in the tables below. table 9: absolute maximum ratings parameter value parameter value v cc voltage -0.5 v to 4.6 v dc input current 20 ma v ccio voltag e -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v storage temperature -65c to +150c latch-up immunity 200 ma lead temperature 300c table 10: operating range symbol parameter military industrial commercial unit min max min max min max v cc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -0 speed grade 0.42 2.03 0.43 1.90 0.46 1.85 n/a -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 speed grade 0.43 0.90 0.46 0.88 n/a -4 speed grade 0.43 0.82 0.46 0.80 n/a
? 2002 quicklogic corporation www.quicklogic.com 9 ql4036 quickram data sheet rev g table 11: dc characteristics symbol parameter conditions min max units vih input high voltage 0.5 v cc v cci o + 0.5 v vil input low voltage -0.5 0.3 v cc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9 v cc v vol output low voltage iol = 16 ma a a. applies only to -1/-2/-3/-4 commercial grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. 0.45 v iol = 1.5 ma 0.1 v cc v ii i or i/o input leakage current vi = v ccio or gnd -10 10 a ioz 3-state output leakage current vi = v ccio or gnd -10 10 a ci input capacitance b b. capacitance is sample tested only. clock pins are 12 pf maximum. 10 pf ios output short circuit current c c. only one output at a time. duration should not exceed 30 seconds. vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current d d. for -1/-2/-3/-4 commercial grade devices only. maximum icc is 3 ma for -0 commercial grade and all industrial grade device and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer applications group (see ). vi, vio = v ccio or gnd 0.50 (typ) 2 ma iccio d.c. supply current on vccio 0 100 a
10 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g kv and kt graphs figure 6: voltage factor vs. supply voltage figure 7: temperature factor vs. operating temperature 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 voltage factor vs. supply voltage supply voltage (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temperature factor vs. operating temperature junction temperature c kt
? 2002 quicklogic corporation www.quicklogic.com 11 ql4036 quickram data sheet rev g power-up sequencing figure 8: power-up requirements the following requirements must be met when powering up the device (refer to figure 8 ): when ramping up the power supplies keep (vccio -vcc) max 500 mv. deviation from this recommendation can cause permanent damage to the device. v ccio must lead v cc when ramping the device. the power supply must take greater than or equal to 400 s to reach vcc. ramping to v cc /v ccio earlier than 400 s can cause the device to behave improperly. an internal diode is present in-between v cc and v ccio , as shown in figure 9 . figure 9: internal diode between vcc and vccio voltage v ccio v cc (v ccio -v cc ) max time 400 us v cc v cc v ccio internal logic cells, ram blocks, etc io cells
12 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g jtag figure 10: jtag block diagram microprocessors and application specific inte grated circuits (asics) pose many design challenges. one of these challenges concerns the accessibility of test points. the joint test access group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir); these allow users to run three required tests, along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
? 2002 quicklogic corporation www.quicklogic.com 13 ql4036 quickram data sheet rev g the jtag 1149.1 standard require s the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (via the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to samp le the functional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. the bypass instruction allows users to test a device without passing through other devices. the bypass register connects the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device.
14 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g pin descriptions ordering information table 12: pin descriptions pin function description tdi/rsi test data in for jtag /ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vcc if unused. trstb/rro active low reset for jtag /ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo/rco test data out for jtag /ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. v cc power supply pin connect to 3.3 v supply. v ccio input voltage tolerance pin connect to 5.0 v supply if 5 v input tolerance is required, otherwise connect to 3.3 v supply. gnd ground pin connect to ground. gnd/therm ground/thermal pin available on 456-pbga only. connect to ground plane on pcb if heat sinking desired. otherwise may be left unconnected. ql 4036 - 1 pq208 c quicklogic device quickram device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow operating range c = commercial i = industrial m = military package code pf144 = 144-pin tqfp cf208 = 208-pin cqfp pq208 = 208-pin pqfp pb256 = 256-pin pbga * contact quicklogic regarding availabliity
? 2002 quicklogic corporation www.quicklogic.com 15 ql4036 quickram data sheet rev g 144 tqfp and 208 pqfp/cqfp pinout diagrams figure 11: top view of 144 pin tqfp figure 12: top view of 208 pin pqfp/cqfp pin 1 pin 37 pin 73 pin 109 ql4036-1pf144c quickram pin 1 pin 53 pin 105 pin 157 QL4036-1PQ208C quickram
16 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g 144 tqfp and 208 pqfp/cqfp pinout table table 13: 144 tqfp and 208 pqfp/cqfp pinout table 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 208 pqfp 144 tqfp function 1nc i/o 43 30 gnd 85 60 i/o 127 87 gnd 169 117 i/o 2 1 i/o 44 31 i/o 86 61 i/o 128 88 i/o 170 118 i/o 32 i/o 45 nc i/o 87 nc i/o 129 89 gclk / i 171 119 i/o 4 3 i/o 46 32 i/o 88 62 i/o 130 90 aclk / i 172 120 i/o 5nc i/o 47 nc i/o 89 63 i/o 131 91 vcc 173 nc i/o 6 4 i/o 48 33 i/o 90 nc i/o 132 92 gclk / i 174 nc i/o 75 i/o 49 nc i/o 91 nc i/o 133 93 gclk / i 175 121 i/o 8 nc i/o 50 34 i/o 92 64 i/o 134 94 vcc 176 nc i/o 96 i/o 51 35 i/o 93 nc i/o 135 95 i/o 177 122 gnd 10 7 vcc 52 36 i/o 94 65 i/o 136 nc i/o 178 123 i/o 11 nc i/o 53 37 i/o 95 66 gnd 137 96 i/o 179 124 i/o 12 nc gnd 54 38 tdi 96 67 i/o 138 nc i/o 180 nc i/o 13 8 i/o 55 39 i/o 97 nc vcc 139 97 i/o 181 125 i/o 14 nc i/o 56 nc i/o 98 nc i/o 140 98 i/o 182 126 gnd 15 9 i/o 57 40 i/o 99 68 i/o 141 nc i/o 183 127 i/o 16 nc i/o 58 nc i/o 100 69 i/o 142 99 i/o 184 128 i/o 17 10 i/o 59 nc gnd 101 nc i/o 143 nc i/o 185 129 i/o 18 11 i/o 60 41 i/o 102 70 i/o 144 100 i/o 186 nc i/o 19 12 i/o 61 42 vcc 103 71 trstb 145 nc vcc 187 130 vccio 20 13 i/o 62 43 i/o 104 72 tms 146 101 i/o 188 131 i/o 21 nc i/o 63 nc i/o 105 nc i/o 147 102 gnd 189 132 i/o 22 14 i/o 64 44 i/o 106 73 i/o 148 103 i/o 190 nc i/o 23 15 gnd 65 45 i/o 107 nc i/o 149 104 i/o 191 133 i/o 24 16 i/o 66 nc i/o 108 74 i/o 150 nc i/o 192 134 i/o 25 17 gclk / i 67 46 i/o 109 75 i/o 151 105 i/o 193 nc i/o 26 18 aclk / i 68 47 i/o 110 76 i/o 152 106 i/o 194 135 i/o 27 19 vcc 69 48 i/o 111 77 i/o 153 nc i/o 195 136 i/o 28 20 gclk / i 70 nc i/o 112 nc i/o 154 107 i/o 196 nc i/o 29 21 gclk / i 71 49 i/o 113 78 i/o 155 nc i/o 197 137 i/o 30 22 vcc 72 nc i/o 114 79 vcc 156 108 i/o 198 nc i/o 31 23 i/o 73 50 gnd 115 80 i/o 157 109 tck 199 138 gnd 32 nc i/o 74 51 i/o 116 nc gnd 158 110 stm 200 139 i/o 33 24 i/o 75 52 i/o 117 81 i/o 159 111 i/o 201 nc vcc 34 nc i/o 76 nc i/o 118 82 i/o 160 nc i/o 202 140 i/o 35 25 i/o 77 53 i/o 119 nc i/o 161 112 i/o 203 nc i/o 36 nc i/o 78 54 gnd 120 83 i/o 162 113 i/o 204 141 i/o 37 26 i/o 79 55 i/o 121 nc i/o 163 nc gnd 205 142 i/o 38 27 i/o 80 56 i/o 122 84 i/o 164 nc i/o 206 nc i/o 39 28 i/o 81 nc i/o 123 85 i/o 165 114 vcc 207 143 tdo 40 nc i/o 82 57 i/o 124 nc i/o 166 115 i/o 208 144 i/o 41 nc vcc 83 58 vccio 125 86 i/o 167 116 i/o 42 29 i/o 84 59 i/o 126 nc i/o 168 nc i/o
? 2002 quicklogic corporation www.quicklogic.com 17 ql4036 quickram data sheet rev g 256 pbga pinout diagram figure 13: 256 pbga pinout diagram ql4036-1pb256c quickram bottom view top view pin a1 corner 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2
18 www.quicklogic.com ? 2002 quicklogic corporation ql4036 quickram data sheet rev g 256 pbga pinout table table 14: 256 pbga pinout table 256 pbga function 256 pbga function 256 pbga function 256 pbga function 256 pbga function 256 pbga function a1 vss c4 i/o e19 i/o l2 aclk / i t17 i/o v20 i/o a2 i/o c5 i/o e20 i/o l3 gclk / i t18 i/o w1 i/o a3 i/o c6 i/o f1 i/o l4 gclk / i t19 nc w2 i/o a4 i/o c7 i/o f2 i/o l17 vcc t20 i/o w3 tdi a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 i/o a6 i/o c9 vccio f4 vcc l19 i/o u2 i/o w5 i/o a7 i/o c10 i/o f17 vcc l20 i/o u3 i/o w6 i/o a8 i/o c11 i/o f18 nc m1 i/o u4 vss w7 i/o a9 i/o c12 i/o f19 i/o m2 i/o u5 i/o w8 i/o a10 i/o c13 i/o f20 i/o m3 i/o u6 vcc w9 i/o a11 i/o c14 i/o g1 i/o m4 nc u7 i/o w10 i/o a12 i/o c15 i/o g2 nc m17 nc u8 vss w11 i/o a13 i/o c16 i/o g3 i/o m18 i/o u9 i/o w12 i/o a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 i/o a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 i/o a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 i/o a17 i/o c20 i/o g19 nc n2 i/o u13 vss w16 i/o a18 i/o d1 i/o g20 i/o n3 i/o u14 i/o w17 i/o a19 tck d2 i/o h1 i/o n4 vss u15 vcc w18 i/o a20 i/o d3 i/o h2 i/o n17 vss u16 i/o w19 i/o b1 tdo d4 vss h3 i/o n18 i/o u17 vss w20 trstb b2 i/o d5 i/o h4 vss n19 i/o u18 i/o y1 i/o b3 i/o d6 vcc h17 vss n20 i/o u19 i/o y2 nc b4 i/o d7 i/o h18 i/o p1 i/o u20 i/o y3 i/o b5 i/o d8 vss h19 i/o p2 i/o v1 i/o y4 i/o b6 i/o d9 i/o h20 i/o p3 i/o v2 nc y5 i/o b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 i/o b8 i/o d11 vcc j2 i/o p17 i/o v4 i/o y7 i/o b9 i/o d12 i/o j3 nc p18 i/o v5 i/o y8 i/o b10 i/o d13 vss j4 i/o p19 nc v6 i/o y9 i/o b11 i/o d14 i/o j17 nc p20 i/o v7 i/o y10 i/o b12 i/o d15 vcc j18 i/o r1 nc v8 i/o y11 i/o b13 i/o d16 i/o j19 i/o r2 i/o v9 i/o y12 i/o b14 i/o d17 vss j20 gclk / i r3 i/o v10 i/o y13 i/o b15 i/o d18 i/o k1 i/o r4 vcc v11 i/o y14 i/o b16 i/o d19 i/o k2 i/o r17 vcc v12 vccio y15 i/o b17 nc d20 i/o k3 i/o r18 i/o v13 i/o y16 i/o b18 stm e1 nc k4 vcc r19 i/o v14 i/o y17 i/o b19 nc e2 i/o k17 gclk / i r20 i/o v15 i/o y18 i/o b20 i/o e3 i/o k18 aclk / i t1 nc v16 i/o y19 i/o c1 i/o e4 i/o k19 gclk / i t2 i/o v17 i/o y20 nc c2 i/o e17 i/o k20 nc t3 i/o v18 i/o c3 i/o e18 i/o l1 gclk / i t4 nc v19 tms
? 2002 quicklogic corporation www.quicklogic.com 19 ql4036 quickram data sheet rev g contact information telephone:408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/ revision history copyright information copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this product brief, and the accompanying software programs are pro- tected by copyright. all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to make periodic modifications of this product without obligation to notify any per- son or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohib- ited. quicklogic, pasic, and vialink are registered trademarks, and spde and quick works are trade- marks of quicklogic corporation. verilog is a registered trademark of cadence design systems, inc. table 15: revision history revision date comments a not avail. first release. b not avail. c not avail. d not avail. e not avail. f may 2000 update of ac/dc specs and reformat g may 2002 added kfactor, power-up, jtag and mechanical drawing information. reformatted.

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